Mask Design Verification
Verification products include both DRC and LVS. The LVS product
includes a compare module to compare the extracted netlist to the
reference netlist. Both products are integrated within the slam
environment. Both are invoked from within slam. The results of the
DRC product are stored in the database and may be reviewed with
VioVue which is part of the slam layout viewer. The LVS product
generates a text error report in addition to the graphical error
report. The LVS product can also generate a netlist from the layout
in spice format.
New in 3.9.0 is the ability to extract parasitic wiring resistance from
the layout. A full RC model of the interconnect wiring can be extracted and
converted to spice. Additionally, graphical display of the wiring
resistance is available and can be cross probed with the spice text file.
Also in 3.9.0 is a new option to the MOSFET device extractor to allow
for source/drain identification for devices that do not have a symmetrical
New in 3.8.2 is a new example and some changes to the existing examples.
Also in 3.8.2 is the Archive Assitant which requires the LVS key to
search the archive for matching netlists.
The assistant searches in 3 easy steps. First
either a schematic or netlist is selected. In this case a simple
nand2 schematic will be found in the archive named "archive" in the current
directory. After "Apply" has been clicked on the search form, the archive is searched and the
results are displayed. After selecting one of the matches and
clicking on "Open Archive" to open the archived copy of the layout, the
layout will be opened in the editor as displayed here.
New in 3.6.1 are several new DRC commands to check edges of shapes
instead of the whole shape. With these latest enhancements, you can check most
0.18 micron processes.
New in 3.5.5 is antenna checking. Top of metal, side wall and cut
ratio checks are supported. Top, side wall and cut can be summed
for a single ratio check, or checked separately. The new antenna
commands can also create the LEF antenna model data to complete
that part of the abstract model.
A few new checks
such as selecting holes of a polygon was also added in 3.5.5.
Note the 3.5.4 release offers a completely new any angle more efficient LVS. The old
code can still be called. As with DRC, the new LVS offers some options the old
LVS did not support such as extracting NRS/NRD, WPE and STI for MOS devices, but the new
code is backwards compatible and can run prior decks unchanged.
The new 3.5.4 code offers some command options not
available in prior releases, but the new code is backwards compatible and can run
prior decks unchanged. Note the new any angle code does not currently
support area mode, only whole cells can be verified.
* Graphical display of errors. In this example the red bars on the
left indicate a spacing violation. The horizontal lines on right
indicate a width violation. snapshot
* Notch fill.
* Width, one and two layer spacing checks, enclosure checks and
* End of line checks for asymetrical via enclosure rules.
* Enclosure check can verify poly extension of active and
active extension over poly.
* Layer density check. (Min and max).
* Polygon selection based on width, area or holes.
* Polygon selection based on compare poly crossing, abutting, inside,
* Selection of polygon hole.
* Polygon selection based on interaction count.
* Edges of polygon selection based on edge overlap with a compare polygon.
* Further subselection of polygon edges based on edge length.
* Metal check deck can be auto-generated from configuration file.
useful to quickly generate check decks for P&R edit checking.
* Antenna check (either area of shape or edge of shape,
accumulative by layer or spacified layer).
* LEF antenna model generation.
* MOSIS DRC deck included.
* LVS includes a interconnect capacitance extractor mode.
* LVS instance extraction mode to extract interconnection
information between blocks or standard cells.
* Generic 4, 5 and 6 layer metal process LVS decks included.