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Below is the verilog followed by the spice for a simple 2 level
schematic hierarchy. The schematics
include the top level schematic and2Group and
2 lower level schematics inv and nand2.
Note the and2Group uses both bus'ed wires and iterated instances.
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// Stabie-Soft Verilog Netlist generator.
// Create time: Tue Sep 30 12:35:48 2008
// Created by user private
// Level 3 cells
// Level 2 cells
// Converted from library foo cell nand2 view sch
// Last modified on Fri Mar 31 12:53:55 2006
module nand2 (vdd, A, B, Y, vss);
inout vdd;
input A;
input B;
output Y;
inout vss;
wire _n0;
nmos M1 (Y, _n0, A, vss);
pmos M2 (Y, vdd, A, vdd);
nmos M3 (_n0, vss, B, vss);
pmos M4 (Y, vdd, B, vdd);
endmodule
// Converted from library foo cell inv view sch
// Last modified on Mon Jun 16 09:13:00 2003
module inv (vdd, A, Y, vss);
inout vdd;
input A;
output Y;
inout vss;
nmos M1 (Y, vss, A, vss);
pmos M2 (Y, vdd, A, vdd);
endmodule
// Level 1 cells
// Converted from library foo cell and2Group view sch
// Last modified on Tue Sep 30 12:35:43 2008
module and2Group (vdd, Y, YBUF, YBUS, A, B, vss);
inout vdd;
output Y;
output YBUF;
output [0:3] YBUS;
input A;
input B;
inout vss;
wire _n1;
wire [0:3] bus;
nand2 X2 (.vdd(vdd), .A(A), .Y(_n1), .vss(vss), .B(B));
inv X3 (.vdd(vdd), .A(_n1), .Y(Y), .vss(vss));
nand2 \IX[0] (.vdd(vdd), .A(A), .B(B), .Y(bus[0]), .vss(vss));
nand2 \IX[1] (.vdd(vdd), .A(A), .B(B), .Y(bus[1]), .vss(vss));
nand2 \IX[2] (.vdd(vdd), .A(A), .B(B), .Y(bus[2]), .vss(vss));
nand2 \IX[3] (.vdd(vdd), .A(A), .B(B), .Y(bus[3]), .vss(vss));
nmos M1 (YBUF, vss, Y, vss);
pmos M2 (YBUF, vdd, Y, vdd);
inv \X5[0] (.vdd(vdd), .A(bus[0]), .Y(YBUS[0]), .vss(vss));
inv \X5[1] (.vdd(vdd), .A(bus[1]), .Y(YBUS[1]), .vss(vss));
inv \X5[2] (.vdd(vdd), .A(bus[2]), .Y(YBUS[2]), .vss(vss));
inv \X5[3] (.vdd(vdd), .A(bus[3]), .Y(YBUS[3]), .vss(vss));
endmodule
=========================================================================================
******************************SPICE******************************************************
=========================================================================================
** Stabie-Soft Spice Netlist generator.
** Create time: Tue Sep 30 14:26:22 2008
** Created by user private
** Level 3 cells
** Level 2 cells
** Last schematic mod time March 31 2006 12:53:55
** Last symbol mod time June 16 2003 09:21:54
** Netlisted from nand2 view sch
** library foo /home/private/test1/secoursExample
.SUBCKT nand2 vdd A B Y vss
****** sub circuit body ******
M1 Y A _n0 vss NMOS W=5e-07 L=1.5e-07 M=2
M3 _n0 B vss vss NMOS W=5e-07 L=1.5e-07 M=2
M2 Y A vdd vdd PMOS W=5e-07 L=1.5e-07 M=4
M4 Y B vdd vdd PMOS W=5e-06 L=2.5e-07 M=2
.ENDS
** Last schematic mod time June 16 2003 09:13:00
** Last symbol mod time May 07 2003 13:08:30
** Netlisted from inv view sch
** library foo /home/private/test1/secoursExample
.SUBCKT inv vdd A Y vss
****** sub circuit body ******
M1 Y A vss vss NMOS W=5e-07 L=1.5e-07 M=1
M2 Y A vdd vdd PMOS W=5e-07 L=1.5e-07 M=1
.ENDS
** Level 1 cells
** Last netlist mod time September 30 2008 12:35:43
** Netlisted from and2Group view sch
** library foo /home/private/test1/secoursExample
.SUBCKT and2Group vdd Y YBUF YBUS[0] YBUS[1] YBUS[2] YBUS[3] A B vss
****** sub circuit body ******
X5[0] vdd bus[0] YBUS[0] vss inv
X3 vdd _n1 Y vss inv
X5[1] vdd bus[1] YBUS[1] vss inv
X5[2] vdd bus[2] YBUS[2] vss inv
X5[3] vdd bus[3] YBUS[3] vss inv
X2 vdd A B _n1 vss nand2
XIX[0] vdd A B bus[0] vss nand2
XIX[1] vdd A B bus[1] vss nand2
XIX[2] vdd A B bus[2] vss nand2
XIX[3] vdd A B bus[3] vss nand2
M1 YBUF Y vss vss NMOS M=1 W=1.2e-06 L=1.5e-07
M2 YBUF Y vdd vdd PMOS W=5e-07 L=1.5e-07 M=1
.ENDS
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